|OUR RESEARCH ACTIVITIES
Our goal is to develop functional materials and control of their interfaces,
for the applications to contribute to the realization of energy-efficient
community. The currently on-going research subjects are as follows.
Material Design and Processes for Highly-Efficient Energy Conversion Devices
High-perfomance power devices are expected to very high-energy efficient
electric conversions. We are now developing novel processes to improve
the SiC based power electronic devices.
1. SiC Power MOSFET Fabrication Process Technologies
- Novel process development for High-quality SiC MOS Interface.
- Analysis of oxide growth kinetics on SiC and oxide structures near interface.
- Control of energy barriers at SiC-metal interfaces.
In thermal oxidation of SiC, oxidation-induced byproduct, carbon, is a possible source of the high density interface state density at SiC/SiO2. Thus a smooth elimination of carbon byproduct from the interface is essentially important to form an ideal interface structure. We are currently working on the precise analysis of oxidation kinetics in nanometer-thick region.
| 仯 A schematic of SiO2 growth by thermal oxidation of SiC. The reduction
of interface defect formation is needed.
||仯 Oxide growth on 4H-SiC(0001) in nanometer-thick region was found to follow
the interface-reaction-limited model (based on accurate determination of
film thickness of nanometer-thick films).
We attained the MOS interface with interface state density as low as below
1011cm-2eV-1 on 4H-SiC (0001) face by the control of thermal oxidation conditions.
This is the world smallest level of the interface state density for 4H-SiC(0001).
The characteristics of MOS capacitor are almost identical with the theoretically
expected ideal ones.
| 仯 C-V (capacitance-voltage乯 characteristics of 4H-SiC (0001). High-frequency
curve is almost identical with an ideal one shown by dotted line.
||仯 Comparison of the interface state density on 4H-SiC with the previously
reported typical values on 4H-SiC. The world-smallest value was demonstrated
in our study (from the press release on July 25, 2014).
At the interface between SiC and the thermally-grown SiO2, we have ultrathin strained-SiO2 layer. The interface with small density
of interface defects is attained by this transition layer formation. It
is crucial to understand the SiC MOS interface microscopic structure to
understand the factors to determine the intrinsic properties of this interface.
| 仯 Significant peak shifts of lattice vibrations of SiO2 for a few nanometer-thick thermal oxides on SiC, caused by the strained structure formation at SiC/SiO2 interface (FTIR-ATR analysis).
|| 仯Strained structure of thermal oxides on SiC within a few nanometer from
the interface strongly depends on the crystal faces of SiC. We found that
the amount of shift of the lattice vibration peaks is quite different between
the oxides on (0001) and (000-1) faces (thickness-dependence of the FTIR-ATR
Press release : Introducing our research results!
Japan Science and Technology Agency乮JST乯 (Jul 25, 2014)
School of Engineering, The University of Tokyo (Jul 28, 2014)
UTokyo Research (Aug 6, 2014)
Material Design and Technologies for Future Ultralow Power Consuming Nano-Electronics
We are doing from basic researches on functional nano-scale stacks and interfaces to device designs for the ultralow-power-consuming advanced electronic devices with novel operation mechanisms.
2. Magnetisms and Interface Design for Ferromagnetic Stacks
- Voltage control of magnetic anisotoropy of ultrathin ferromagnets
(Joint research with IBM T. J. Watson Research Center)
Ferromagnetic stacks with perpendicular magnetic anisotorpy are useful
in electron devices, which is often realized by using ultrathin ferromagnetic
films as thin as ~1 nm to enhance the effects of interface magnetic anisotropy.
The magnetic anisotropy of oxide/ferromagnetic stacks sensitively changes
by both structure and composition at the interface. We are surveying the
important factors to determine the properties of this interface to develop
a guideline to control the interface magnetic anisotropy.
The voltage application can change the interface magnetic ansiotropy. This
phenomenon may lead us to develop a new kinds of spintronics devices including
ultralow-power-consuming memory devices. We are investigating the way to
design the interface to maximize this effect.
| 仯 Depth profile change of MgO/CoFeB 乮乣1nm)/Ta stacks by thermal treatment.
We clarified that Ta diffusion has a siginificant impact on interface anisotropy
energy (HR-RBS analysis).
||仯 Voltage-induced change of magnetization behavior of Ru/Al2O3(10nm)/MgO(1nm)/CoFeB
乮1.2nm)/Ta stack due to the change of interface magnetic anisotropy. The
response to the out-of-plane field is compared for the cases with -8 V
and +6V application between Ru and Ta 乮collaborative study with IBM T.
J. Watson Research Center乯.
3. Dielectric Properties and Interface of Ultrathin High-k Oxides
- Material design of high-k (high dielectric constant) oxides for CMOS
- Understanding the phenomena at oxide interface, such as interface dipole
layer formation which contributes to the threshould voltage control of
Electron potential barrier sometimes appears at the interface between two
kinds of oxides by "interface dipole effect", even those two
materials are insulators without free electrons. This interface effect
has an important role in MOS devices, in the control of threshould votage
of transistors. We are investigating the physical origin of the dipoles
to establish a guideline to control this phenomenon.
| 仯Schematic image of the interface dipole layer between high-k dielectric
and SiO2 on Si (for the case of dipole from high-k toward SiO2).
||仯 Strength of the interface dipole effect between high-k and SiO2 seems
to correlate with areal density of oxygen atoms in high-k materials. The
microscopic structural property of high-k oxides should be one of the important
factors to detemine the dipole effects.
4. Optically-Functional Oxide Semiconductor Stacks
- Material designs for all-oxide electrochromic devices